Analysis of floating substrate effects on the intrinsic gate capacitance of SOI MOSFETSs using two-dimensional device simulation

Abstract

Points out that the theoretical foundation of unique floating substrate effects, which have been observed experimentally, on the intrinsic gate capacitance characteristics of SOI n-MOSFETs has been clearly established using original two-dimensional device simulations. A transient simulation scheme for calculating intrinsic capacitances is introduced and tested against the classical quasi-static and small-signal analyses. The results are discussed and used to gain a deep physical insight into the basic mechanisms responsible for the anomalous (when compared to conventional bulk devices) intrinsic capacitances observed in the case of SOI MOSFETs. The analyses yields basic guidelines for an adequate analytical modeling of SOI MOSFET capacitive behavior to be used for accurate large- and small-signal simulation of SOI MOS digital and analog circuits. >