Abstract
A Negative Word Line (NWL) bias scheme is an effective method to reduce the junction leakage current of DRAM cell transistor by reducing the channel implantation dose used to adjust the threshold voltage. However, the static data retention characteristics might be degraded by the GIDL current due to increasing E-filed between the gate and the drain in off-state. In addition, it could cause degradation of the dynamic data retention characteristics by occurring negative word line bias (VNWL) fluctuation during DRAM chip operation, because of increase of the sub-threshold leakage current of cell transistor. This paper gives a detailed analysis of the problem on the dynamic chip test in NWL scheme, especially for the Refresh Cycle Reduction (RCR) mode test and suggests the design guideline for the chip test.
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