Abstract
Shift registers are finding superior claim in the design of applications specific architectures. Latches are basic functional elements in the design of shift registers and are basically storage elements that store data and it is an asynchronous circuit. The conventional DICE (Dual Interlocked Storage Cell) induces an error (Single Event Upset) during fabrication. To overcome this problem DICE latch with feedback is proposed and shift register is designed using both the latches. The result of shift register with feedback DICE latch is compared with shift register with DICE latch in terms of power and concluded that the proposed shift register with feedback DICE latch error performance is better than shift register with DICE latch.
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