Abstract
AbstractIn this paper, a delay fault model for multilayer graphene nanoribbon (GNR)‐based power interconnects for 16‐nm International Technology Roadmap for Semiconductors technology node is developed for both top‐contact GNR and side‐contact GNR. The delay fault model is developed for different temperature considering the impact of scattering parameters. It is shown that side‐contact GNR‐based power interconnects can reduce the delay fault significantly in comparison with that of Cu and top‐contact GNR interconnects at local, intermediate, and global lengths for a wide range of chip operating temperatures from 233 K to 378 K.
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