Abstract
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under off -state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant on-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I- V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
