Abstract

Trap levels which are deep or shallow play an important role in the electrical and the optical properties of a semiconductor; thus, a trap level analysis is very important in most semiconductor devices. Deep-level defects in CdZnTe are essential in Fermi level pinning at the middle of the bandgap and are responsible for incomplete charge collection and polarization effects. However, a deep level analysis in semi-insulating CdZnTe (CZT) is very difficult. Theoretical capacitance calculation for a metal/insulator/CZT (MIS) device with deep-level defects exhibits inflection points when the donor/acceptor level crosses the Fermi level in the surface-charge layer (SCL). Three CZT samples with different resistivities, 2 × 104 (n-type), 2 × 106 (p-type), and 2 × 1010 (p-type) Ω·cm, were used in fabricating the MIS devices. These devices showed several peaks in their capacitance measurements due to upward/downward band bending that depend on the surface potential. Theoretical and experimental capacitance measurements were in agreement, except in the fully compensated case.

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