Analysis of clock buffer phase noise

Abstract

Clock buffers are widely used in microprocessors and other synchronous communication chips in which a global clock signal is distributed throughout the chip. This paper presents a phase noise model for clock buffers. The model can be used to predict the phase noise introduced by clock buffers and to gain insight into phase noise transfer mechanisms in clock buffers. Based on the models, techniques for low phase noise clock buffer design are derived. The analytical results presented here have good agreement with simulation and measurement results.