Abstract
In this paper, an analysis of basic Current Mirror (CM) topologies was performed with a focus on comparison of conventional realization to Bulk-Driven (BD) and Dynamic-Threshold (DT) equivalents, in terms of main properties. These circuits were designed in 130 nm CMOS technology using the supply voltage of 0.6 V and laid out on a test-chip. Fabricated circuits were analyzed and their characteristics compared to the simulation results. The achieved results prove that these unconventional circuit design techniques are quite promising for contemporary ultra low-voltage analog Integrated Circuits (ICs)
Highlights
Introduction and BackgroundNowadays, lot of research effort has been encouraged to develop design techniques for low-voltage analog Integrated Circuits (ICs) in standard CMOS process in order to avoid circuits to be the limiting factor of the power supply voltage downscaling
Using gmb transconductance instead of gm decreases the overall device transconductance and increases the input capacitance, which is from 3 to 5 times larger than the input capacitance of a GD MOS transistor [7]. This can lead to lower Gain Band-Width (GBW) and worse frequency response ft(BD) in comparison to the transit frequency ft(GD) of a conventional GD MOS device
Another benefit is improving the Input Common-Mode Range (ICMR) which can result in full rail-to-rail IMCR [10] topologies
Summary
Lot of research effort has been encouraged to develop design techniques for low-voltage analog ICs in standard CMOS process in order to avoid circuits to be the limiting factor of the power supply voltage downscaling. The main idea behind the BD design technique is in the structure of the MOSFET, where the bulk terminal is used as the signal input In such a configuration, the transistor threshold voltage can be reduced with no modifications of the MOSFET structure or technology process. Using gmb transconductance instead of gm decreases the overall device transconductance and increases the input capacitance, which is from 3 to 5 times larger than the input capacitance of a GD MOS transistor [7]. This can lead to lower Gain Band-Width (GBW) and worse frequency response ft(BD) in comparison to the transit frequency ft(GD) of a conventional GD MOS device. The transit frequency for the BD MOS transistor and the GD MOS device is expressed in Eq (3) and Eq (4), respectively
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