Analysis of Active-Clamp Response to Power-On ESD: Power Supply Integrity and Performance Tradeoffs

Abstract

An active rail clamp circuit provides protection against component-level ESD; this work explores the challenges associated with designing a rail clamp to additionally provide protection when the IC is powered on. The fast transient response required to protect against ESD makes it difficult to design a stable circuit and introduces tradeoffs between supply integrity and the clamping characteristic. This work presents an analysis of how these performance metrics are affected by device sizes. Interactions between a rail clamp circuit, which may be an active or passive clamp, and the parasitic elements of the package and board are examined; it is shown that these interactions may briefly power down the supply.