Analysis of a packet switch with memories running slower than the line-rate

Abstract

Our work is motivated by the desire to build a very high speed packet switch with extremely high line-rates. In this paper, we consider building a packet switch from multiple, lower speed packet switches operating independently and in parallel. In particular, we consider a (perhaps obvious) parallel packet switch (PPS) architecture in which arriving traffic is demultiplexed over k identical, lower speed packet-switches, switched to the correct output port, then recombined (multiplexed) before departing from the system. Essentially, the packet switch performs packet-by-packet load-balancing, or inverse-multiplexing over multiple independent packet switches. Each lower-speed packet switch, operates at a fraction of the line-rate, R; for example, if each packet switch operates at rate R/k no memory buffers are required to operate at the full line-rate of the system. Ideally, a PPS would share the benefits of an output-queued switch; i.e. the delay of individual packets could be precisely controlled, allowing the provision of guaranteed qualities of service. In this paper, we ask the question: Is it possible for a PPS to precisely emulate the behavior of an output-queued packet-switch with the same capacity and with the same number of ports? The main result of this paper is that it is theoretically possible for a PPS to emulate a FCFS (first come first served) output-queued packet-switch if each layer operates at a rate of approximately 2R/k. This simple result is analogous to Clos theorem for a three-stage circuit switch to be strictly non-blocking. We further show that the PPS can emulate any QoS queueing discipline if each layer operates at a rate of approximately 3R/k.