Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Controller Design with Resistive Random-Access Memories (RRAM) for Field-Programmable Gate Arrays (FPGA)

Abstract

This paper studies the simulation results of a novel controller circuit design for non-volatile (NV) look-up tables (LUT) combined with an electrical model of a resistive random-access memory (RRAM)—an emerging non-volatile memory (NVM) device. The Write and Read schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully switches between low ‘0’ and high ‘1’ while the unselected the RRAM remain undisturbed, demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs. Reading of a selected RRAM is also performed with agreeable results.