Abstract
As complementary metal-oxide semiconductor (CMOS) technologies move to below 10 nm due to aggressive scaling, a new device structure is required to increase gate controllability for mitigating short- channel effects (SCEs). In this study, a 3D technology computer-aided design (TCAD) tool is used to analyze three different channel shapes of gateall- around (GAA) nanowires: circular, square, and trapezoidal. Simulation results show that the trapezoidal channel shape provides the maximum on-current from among the three shapes for the same cross-sectional area. In addition, the trapezoidal nanowire shows the minimum leakage current. In the trapezoidal shape, more benefits in both on- and offcurrent are expected when the ratio between top and bottom widths increases. Carrier density profiles in TCAD simulations reveal that the current variation is due to the channel shape and the electrical property of the channel.
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