Analysis, Modeling, and Mitigation of Parasitic Resonances in Integrated Metallic Seal Rings

Abstract

The cause of a measured −1.4-dB dip at 80 GHz in a silicon capacitor was investigated and determined to be the primary resonance of the integrated metal seal ring (SR) enclosing the component. Specifically, the proximity of a capacitor electrode to the SR was found to activate two parasitic, parallel, and open-circuited coplanar strip transmission lines (TLs), each having their ${\lambda /2}$ resonance at this frequency. This model was confirmed with 3-D finite-element method electromagnetic simulations and measurements of modified SRs. Building on the proposed TL interpretation of the problem, an ultra-broadband equivalent circuit model was developed for such capacitors, successfully replicating the measured SR resonance. Then, the fundamental resonance frequency and related quality factor of various-sized integrated metal SRs were accurately predicted. Finally, potential solutions to damp or cancel such parasitic resonances were investigated. Although cutting the SR at selected locations to disable the parasitic lines was experimentally proven to be successful, damping the parasitic signal with highly doped silicon is found to be the best option in terms of effectiveness and practical implementation. Novel solutions, analogous to the use of radio frequency terminations, were also tested. This paper, to the best of our knowledge, is the first extensive characterization of parasitic resonance afflicting electronics enclosed by an integrated metal SR. The analysis, equivalent circuit model, and solutions reported here can be directly applied to arrays of components or circuits, and are scalable to any device size and operating frequency.