Abstract
Today most of the system on chip (Soc) integrate multiple processing cores, digital signal processors, as well as dedicated hardware accelerators, etc [1]. This results into large and complex systems which pose challenges to conventional design and verification flow. This raises the need for higher level of abstraction (i.e. Electronics system level abstraction). This paper discusses how we can make changes in an existing conventional method of simulation to achieve really fast high yielding method of verification. The model is implemented using SystemC and Vlang. The results demonstrate the impact of enabling multiple simulators for verification of hardware models.
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