Analysis and Validation of Low-Frequency Noise Reduction in MOSFET Circuits Using Variable Duty Cycle Switched Biasing

Abstract

In MOS transistors, low-frequency noise phenomena such as random telegraph signal (RTS), burst, and flicker or $1/f$ noise are usually attributed to the random nature of the trap state of defects present at the gate Si-SiO2 interface. In a previous work, theoretical modeling and analysis of the RTS and 1/ $1/f$ noise in MOS transistor was presented and it was shown that this 1/ $1/f$ noise power can be reduced by decreasing the duty cycle ( $D$ ) of switched biasing signal. In this paper, an extended analysis of this 1/ $1/f$ noise reduction model is presented and it is shown that the RTS noise reduction is accompanied with shift in the corner frequency ( ${f}_{c}$ ) of the 1/ $1/f$ noise and the value of shift is a function of continuous ON time ( $T_{on}$ ) of the device. This 1/ $1/f$ noise reduction is also experimentally demonstrated in this paper using a circuit configuration with multiple identical transistor stages which produce a continuous output instead of a discrete signal. The circuit is implemented in 180 nm standard CMOS technology, from UMC. According to the measurement results, the proposed technique reduces the 1/ $1/f$ noise power by approximately 5.9 dB at switching frequency ( ${f}_{s}$ ) of 1 KHz for 2 stage, which is extended up to 16 dB at ${f}_{s}$ of 5 MHz for six stage configuration.