Analysis and reduction of on-chip inductance effects in power supply grids

Abstract

Power supply integrity has become a critical concern in modern chip design. To date, analysis of so-called LdI/dt drop in supply networks has mostly focused on inductance of the package, which is the predominant factor in inductive voltage drop. However, with increased clock frequencies and power supply demands, on-chip inductance has become a significant factor in the total LdI/dt drop. In this paper, we analyze the impact of on-chip inductance on power supply integrity and propose methods that significantly reduce the voltage drop caused by on-chip inductance. We develop a detailed model of a flip-chip supply network based on an industrial design. The model includes an accurate package model, a PEEC (partial electrical equivalent circuit)-based model of the on-chip supply interconnects and both intrinsic and explicit on-chip decoupling capacitance. We show that on-chip inductance can account for up to 30% of the total voltage drop in the GHz processor domain and propose two new on-chip power supply topologies that reduce the on-chip LdI/dt drop by around 70%.