Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing

Abstract

This paper examines the concept of multisection capacitive digital-to-analog converters (MS-CDACs), which enables a wider range of CDAC section segmentation options beyond split-CDAC and C–2C methods. In order to study the proposed approach, analysis and simulations are first conducted for all possible section arrangements of a 6-bit resolution MS-CDAC with minimum-sized unit capacitors; the study shows that MS-CDAC provides various options with reduced total capacitance compared to a single-section CDAC, and allowing for the tradeoff of area, switching energy, and speed versus static linearity and kT / $C$ noise. Thus, it is possible to find a structure that minimizes total capacitance while satisfying required static linearity and noise that cannot be achieved with the existing methods. Compensation of nonlinearities due to parasitic capacitance is accomplished by sizing the bridge capacitance(s). To verify effectiveness in a more practical design scenario, this approach is applied to a 10-bit MS-CDAC design. Using metal–insulator–metal capacitors available in a standard CMOS technology, under the condition that 95% of Monte Carlo simulation results have at most 0.5 LSB of |DNL|, the selected 10-bit MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively, and MSB capacitance by a factor of 26 relative to the single-section CDAC. The postlayout simulations were also conducted to validate the MS-CDAC approach, achieving $\vert \text {DNL}\vert _{\mathrm {max}}$ in the presence of additional layout parasitics.