Abstract

Static random-access memory (SRAM) is an essential component for realizing large-scale integration (LSI). The future transition to a 48 V DC supply in datacenters and electric vehicles acting as mobile edge servers will increase the demand for a bipolar-complementary metal-oxide semiconductor-double diffused metal-oxide semiconductor with high-capacity SRAM. When we scaled and optimized an SRAM cell from 130 nm nodes to 90 nm nodes, we observed the generation of crystal defects induced by mechanical stress in the p-channel MOS active area that cannot be explained by previous models. We performed simulations using the finite element method to identify the mechanism. In our results, the edge of the narrow active area showed a large deformation compared to the middle of the active area, which can be attributed to compressive stress from the gate electrode and sidewall. The cell layout and sidewall structure were optimized to suppress this defect generation while satisfying reliability requirements, and the design can be extended to 65 nm nodes.

Highlights

  • T HE advancement of the Internet of Things has led to a data explosion, with the annual data generation predicted to exceed 175 ZB by 2025 [1]

  • This region overlaps with the gate electrode, which indicates that mechanical stress by the gate electrode may be a root cause for this displacement

  • Finite element simulations were performed to analyze the mechanical stress induced by defects generated in static random-access memory (SRAM) cells

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Summary

INTRODUCTION

T HE advancement of the Internet of Things has led to a data explosion, with the annual data generation predicted to exceed 175 ZB by 2025 [1]. The explosive increase in the power consumption of datacenters has become. A typical approach to minimizing power consumption is to reducing the supply voltage, and the introduction of a 48V DC supply for data buses is being studied intensively [3]–[5]. Compatibility with a 48V DC is becoming a requirement for an increasingly wide range of applications. The bipolar-complementary metal-oxide semiconductor-double diffused metaloxide semiconductor (BiCDMOS) is a technology that combines analog, digital and high voltage devices in a single die [7], and it has been used in the automotive, aerospace and other industrial fields for power management. The BiCDMOS is more economical in the range of

Cell layout comparison
Validation by hardware
PROCESS FLOW AND SIMULATION SETUP
Mechanical stress and defect generation model
F L3S 4EI
Cell layout optimization for 90nm node
50 SC fail
CONCLUSION
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