Analysis and optimization of a novel CMOS multiplier

Abstract

AbstractA novel CMOS voltage multiplier is proposed which is based on MOS transistors in the saturation region and uses a resistor load. A pencil‐and‐paper optimized design procedure and a detailed analysis of second‐order non‐idealities which affect the multiplier core are given. The circuit has been designed with a 1.2 µm CMOS process setting a 3 V power supply and simulations have been performed to validate results. Copyright © 2001 John Wiley & Sons, Ltd.