Abstract
In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS.
Highlights
With the rapid development of integrated circuits and the emergence of advanced process nodes, the data transfer rate of high-speed serial interfaces has grown exponentially [1]
The blue line with circles represents the error jitter of a clock and data recovery (CDR) operating on 56 Gbps of serial data
We present a linear model of the MM-CDR
Summary
With the rapid development of integrated circuits and the emergence of advanced process nodes, the data transfer rate of high-speed serial interfaces (i.e., serializer/deserializer) has grown exponentially [1]. These studies only apply the MMPD without a systematic analysis of the MM-CDR, affecting the circuit design performance and extending the circuit design cycle. As the data transfer rate increases, oversampling designs encounter performance bottlenecks in terms of clocking and power consumption, and the Mueller–Muller baud rate sampling becomes the sampling method at high speed. The error sampler first compares the input data stream (Din) with the threshold voltages “+Vref” and “−Vref” to generate the signals of Errp and Errn. Compared to BBPD, MMPD reduces the time axis constraint but adds two voltage thresholds to obtain the amplitude information of the sampling points (namely Errp and Errn), which detects the phase of the input data applying the amplitude information together with the waveform.
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