Abstract
Two stage quantization is a well-known but still very popular model for signal processing. However, in a number of occasions we have information about a discrete entrance and we do not know the nature of the continuous signal which preceded it. Hence, information source is commonly modelled by using Laplacian or Gaussian distribution but designed quantizers often do not match entire signal range. A typical analysis for discretized input signal does not consider the changes of the continuous signal variance. The aims of this paper are providing an improved analysis by introducing a novel measure CDSVR, designing the second stage quantizer, as well as estimating system performance for mismatched variances. This way, we discuss the influence of A/D conversion on the signal variance and propose an improved model for performance estimation.DOI: http://dx.doi.org/10.5755/j01.eee.21.3.10380
Highlights
Mismatch quantization has become very popular in recent years and its importance and appliance was researched in a number of papers [1]–[6]
It is generally considered that two stage quantization model is such that first quantizer has a smaller number of quantization levels in comparison to the second quantizer
In order to estimate a difference between continuous signal variance of original signal and variance of discretized signal obtained after processing with Q1 we introduce a novel measure: continuous – to – discrete – signal – variance ratio (CDSVR)
Summary
Mismatch quantization has become very popular in recent years and its importance and appliance was researched in a number of papers [1]–[6]. It is generally considered that two stage quantization model is such that first quantizer has a smaller number of quantization levels in comparison to the second quantizer (i.e. required number of bits for transmission is higher for the second quantizer). This way, first quantizer determines the region and the second one determines the level within it [7]–[9]. In [8] was concluded that such two stage quantization model should be designed so that second quantizer is described with at least 4 bits lower number of levels in comparison to the first quantizer. We propose an improved quantization model and performance estimation that will take into account aforementioned problem
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