Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

Abstract

A continuous-time 7-tap FIR equalizer tailored to dispersion compensation in multi-mode fiber links is presented. By using a novel active delay line, the ultra-compact equalizer is very flexible, maintaining optimal performances and power scalability over a wide range of input data-rates. Particular care is taken to address critical issues of continuous-time realizations, such as noise, linearity and dynamic range. All-pass stages, realized with a simple circuit topology featuring high linearity and wide bandwidth, are investigated to implement the active delay line elements. Filter tap coefficients are realized with programmable transconductors and output currents are summed through a transimpedance amplifier, providing simultaneously high gain and wide bandwidth. Extensive experimental results, carried out on test chips realized in 28 nm LP CMOS technology, are presented. The equalizer demonstrates successful operation with variable data-rates ranging from 10 Gb/s to 25 Gb/s and power dissipation scalable from 55 mW to 90 mW. Compared to previously reported high-speed FIR equalizers, the proposed solution accepts the largest variation of the input data-rate with state-of-the-art power efficiency and core silicon area of only 0.085 mm 2 , meeting the demand of emerging 400 Gb/s standards.