Analysis and Design of a Duty-Cycle-Controlled Amplitude Shift Keying Class-E Power Amplifier

Abstract

This paper presents a method for implementing amplitude modulation in class-E power amplifiers (PA). The output voltage amplitude of a class-E PA is proportional to the input signal duty cycle. The proposed method exploits this feature in order to implement amplitude shift keying (ASK) modulation in the standard class-E power amplifier. The conditions for the optimum operation of a class-E PA while using two different input duty cycles are analyzed. The desired conditions are derived at the same time to reduce differences between optimum circuit elements while using different input duty cycles. The resulting class-E PA satisfies both zero voltage switching (ZVS) and zero derivatives of voltage at switching (ZDVS) conditions by changing only one capacitor. This method neither degrades the efficiency nor needs many changes in circuit components. A step-by-step design procedure based on the proposed method is introduced. The simulations and measurement results verify the accuracy of the proposed method. The fabricated PA is designed to operate at 1MHz frequency with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 2V and 50Ω load. The input duty cycle is changed from 25% to 49%, resulting in output amplitudes of 1.2Vpp and 3.68Vpp, and efficiencies of 88% and 94%, respectively.