Analysis and Design of a 5G Multi-Mode Power Amplifier using 130 nm CMOS technology

Abstract

This work proposes a dual-mode radio frequency (RF) power amplifier (PA) for the 4.8 GHz multi-standard applications using a 130 nm CMOS technology. The proposed RF power amplifier (PA) consists of two stages (driver and power). By changing the driver and the power stages bias voltages any mode of PA (class-AB\F) can be achieved. The class-AB or linear mode power amplifier design is appropriate for IoT, LTE, 5G, and multi-standard RF transmitters. Whereas the class-F or switching mode PA is suitable for IoT-LPWAN and Bluetooth applications. The class-AB mode has a saturated output power of 23 dBm at 4.8 GHz, a power-added efficiency (PAE) of 29.5 %, an output third-order intercept point (OIP3) equals 18 dBm, and for LTE 15MHz channel bandwidth the adjacent channel power ratio (ACPR) is -36 dBc. On the other hand, the maximum PAE is 28% and the output power equals 22.3 dBm for the class-F mode. The proposed power amplifier occupies 0.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of the chip area where the active area equals 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power dissipation is 136 mW or 26 mW in the proposed class-AB or class-F PA modes, individually.