Analysis and Design of a 0.3-THz Signal Generator Using an Oscillator-Doubler Architecture in 40-nm CMOS

Abstract

This paper presents the analysis and design of an oscillator-doubler architecture which is used to generate THz signals. In this architecture, the doubler obtains the optimum fundamental-frequency load impedance for second harmonic generation without causing problems related to instability. The oscillator creates voltages close to the optimum voltage condition, which leads to maximum power being delivered to the doubler connected to the oscillator tank. Compared to a signal generator composed of an oscillator and a conventional doubler with short-circuit load at the fundamental frequency, the proposed circuit has higher output power and DC-to-THz conversion efficiency. Based on this architecture, a 0.3-THz signal generator is designed in 40-nm CMOS. In this 0.3-THz signal generator, an inductor-sharing configuration is proposed to increase the transistor size in the cross-coupled oscillator, thus increasing the power density of the signal generator. Besides, the impact of the doubler fundamental-frequency load impedance on the conversion gain of the doubler is introduced. Also, a method of suppressing the unwanted mode in the cross-coupled oscillator is proposed. The output of this circuit is radiated through on-chip antennas. The measured radiated power and the DC-to-THz efficiency of the chip are -3.8 dBm and 0.37%, respectively, with an output frequency tuning range of 4.8%.