Analysis and Countermeasures of Harmonic Instability in a Practical HVDC System with Fixed Series Compensation and STATCOM

Abstract

In a practical ±500 kV/3000 MW line commutated converter based high voltage DC (LCC-HVDC) transmission system, a sustained 5.5/105.5 Hz harmonic was observed in the voltage of the AC bus of inverter station. HVDC power limit function was triggered because of the action of AC filter resistance harmonic overload protection caused by the harmonic. To study the phenomenon, the real-time digital and physical closed-loop simulation platform based on real time digital simulator (RTDS) is first built and the harmonic instability phenomenon is reproduced. Then, its mechanism and impact factors are analyzed based on real-time simulation. Analyses results show that series resonance and core saturation are the main reasons of harmonic. AC/DC harmonic transfer characteristic through converter leads to the interaction of AC and DC network, and inappropriate AC/DC impedance results in the sustained harmonic. Bypassing the series capacitor is proposed as a temporary countermeasure and verified by on-site test. To solve the problem thoroughly, supplementary harmonic controller (SHDC) based on STATCOM is designed, whose validity is verified by simulation tests.