Analyses of phase noise reduction techniques in CMOS Colpitts oscillator topology at the mm-waves: Noise filter and optimum current density

Abstract

This paper reports the analyses of two techniques for phase noise reduction in the CMOS Colpitts oscillator circuit topology. Namely, the two techniques: noise filter and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The design of the circuit topology is carried out in 28 nm bulk CMOS technology. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 17 dB at a 1 MHz frequency offset for an oscillation frequency of 100 GHz.