Analogue and VLSI implementation of connectionist network for minimum spanning tree problems

Abstract

Owing to the fundamental nature and a broad range of applications, minimum spanning tree problems have been widely studied in the field of network flows. Most of the previous works reported are sequential or synchronous parallel algorithms which have a polynomial time dependence on the problem size. This paper describes a connectionist architecture based on the binary relation inference network, which can be implemented as a uniform feedback arrangement using conventional maximum and minimum circuits as basic building blocks. The network has shown promise in obtaining the global optimal solution in a timeindependent of the problem size. This is due to the parallel and asynchronous operating nature of the network, and each computational unit can process information asynchronously, or in the continuous-time domain, without the need of precise synchronization with other units of the network. A particular implementation uses commonly available analogue electronic components, and the network is able to give the global optimal solution within the microseconds range. In addition, the voltage-mode approach using analogue VLSI design techniques in implementing the network is presented. The limiting factors of the performance of the analogue and VLSI implementation circuit are discussed.