Abstract
This work presents a novel low-power CMOS implementation for fast statistical feature extraction from time series. Machine learning (ML) models have become standard for time series processing, however, need to rely on a statistical feature extraction stage. Low power statistical feature extraction from time series has received limited attention despite its central role. Addressing this gap, we present a CMOS-based nonparametric statistical feature extraction. We exploit hardware-level opportunities in the analog domain, such as eliminating additions by current outputs and simplifying kernel cells. We also leverage algorithmic opportunities to utilize continuous-domain sample integration to downsample time series without affecting accuracy. Our propositions are experimentally verified using TSMC 65nm test chip and show 17–75 × lower energy than an advanced digital design on various statistical features. While analog processing is susceptible to non-idealities, co-designing the downstream ML model against such non-idealities can retain accuracy to benefit from the analog domain's area/energy efficiency.
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