Abstract
Analog circuit implementations of decision-directed timing recovery for partial response maximum likelihood (PRML) detectors for disk drives are investigated. First, the basic equations and block diagrams are examined. The parts of the behavioral simulations of the analog system that have significant impact on choosing a topology are discussed. Our results indicate that analog implementations of decision-directed LMS timing recovery are feasible. We anticipate that these implementations will provide higher speed operation at lower power than digital implementations in a comparable technology.
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