Abstract
All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employing these multipliers, large-scale artificial neural networks can be implemented using fewer MOS transistors than are required by implementations employing the so-called Gilbert multiplier. PSPICE circuit simulations have been extensively executed in order to quantify the performance of these multipliers by measuring the following specifications: maximum percentage error, output offset, X or Y nonlinearity, X or Y feedthrough, small-signal bandwidth, and slew rate. An 11-dimensional analog vector multiplier has been designed on a 40-pin MOSIS TINYCHIP with analog pads using the MAGIC VLSI tools and has been fabricated using 2 μm CMOS n-well process via MOSIS.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
