Analog iterative decoding of error control codes

Abstract

Since their introduction in 1993, turbo codes and iterative decoding have made a significant impact in the area of coding theory by providing for the first time near Shannon limit decoding at practical hardware complexity levels. Turbo codes and other iteratively decoded codes have recently been incorporated into several digital communications standards such as DVB-RCS, DVB-RCT, and 3GPP. Because of the iterative nature of the decoding algorithm, turbo decoders are prone to long decoding latency and large power consumption. For these reasons, much research has been directed toward developing novel turbo decoder architectures in order to make them viable for power and speed-conscious applications such as wireless products. This paper presents a review of analog iterative decoding techniques. A family of simple analog circuits used to implement soft-output decoding algorithms will be discussed. Challenges in the design of analog decoders, such as mismatch and input interfaces will also be addressed. Finally, a survey of existing analog decoder integrated circuits will be presented.