Analog design in deep submicron CMOS processes for LHC

Abstract

Present state-of-the-art CMOS technologies integrate MOS transistors with a minimum gate length of 0.18 Pm0.25 Pm and operate with a maximum power supply of 2.5 V. The thin gate oxide used in these technologies has a high tolerance to total dose effects. Therefore, circuits designed in these technologies using dedicated layout techniques (enclosed layout transistors and guard-rings) show a total dose resistance complying LHC specifications [1]. Some of the integrated circuits for LHC have moreover strict requirement on integration and low power consumption, especially in the inner parts of the detectors. A deep submicron technology is therefore a very suitable choice for digital ASIC design, whereas its use for analog and mixed-mode circuits must be investigated more carefully. Commercial submicron technologies are in fact mainly intended for large volume digital applications. The data available from the manufacturers concerning properties like noise and matching may be not completely satisfactory from the analog designer’s point of view. The power supply allowed by a typical 0.25 Pm technology (2.5 V) is almost at the edge of the use of standard analog design techniques. This is of particular concern, for instance, for circuits like switched capacitors analog memories, which are extensively used in high energy physics applications. A submicron technology offers however attractive features also to the analog designer. The many layers of interconnects can be used to improve the quality of analog signals, especially in mixed-mode designs. Due to the squeezed design rules, also density can improve, though not in the same proportion as for digital circuits. The aim of this work is to investigate the analog performances of commercial 0.25 Pm CMOS technologies. In section 2 we discuss the main design aspects which have to be considered in using a deep submicron technology for analog and mixed-mode design. Section 3 describes the test structures we have designed to investigate the analog performances of the technologies and in section 4 measurements performed on such structures are presented.