Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration

Abstract

Peak detectors (peak-detect-and-hold circuits, PDHs) are a key element in nuclear electronics signal processing and have been incorporated as a fully integrated block in several front-end readout chips. In CMOS designs, the PDH uses an MOS current source as the rectifying element inside the feedback loop of a high-gain amplifier. However, the non-idealities in the amplifier and feedback elements significantly limit its accuracy and stability. This paper reports on the limits of the classical CMOS PDH. Static errors due to offset, finite gain, and common-mode rejection, dynamic errors due to parasitic capacitive coupling and slew rate, and loop stability are analyzed. Expressions for each error source and consequent design tradeoffs between accuracy, speed, and dynamic range, and driving capability are derived. In a related article (Part 2), a two-phase PDH configuration, which overcomes the major limits of the classical approach is presented.