Abstract

Several analog circuit design has been suggested where a layout generator is used after a circuit sizing. But, many iterations between circuit sizing and layout generator stages are needed to obtain desired specifications. This paper proposes a new equation and simulation-based method for circuits sizing of CMOS operational amplifiers (op-amps) by considering layout effects. In the proposed method, layout effects are considered during the sizing step. Layout effects are devices parasitics and geometry information that are extracted from a new automated layout generator. Optimization is performed using multi-objective evolutionary algorithm based on decomposition (MOEA/D). In order to evaluate the performance of the proposed sizing method, the design of folded-cascode and three-stage op-amps are provided in a 0.18µm process CMOS technology with 1.8 V supply voltage. The simulation results exhibit the good performance of the proposed sizing method.

Highlights

  • Designing of analog integrated circuits includes three phases: topology selection, circuit sizing and layout extraction [1,2,3,4]

  • Multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as optimizer

  • The devices to be placed on the floorplan are represented by k blocks M1 ..., Mk The objective function is defined for the placement stage as follows: f P = f oP1 (x )

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Summary

Introduction

Designing of analog integrated circuits includes three phases: topology selection, circuit sizing and layout extraction [1,2,3,4]. Some of the layout parasitics are not considered In another method, the sizing is performed by a knowledge-based tool using the equations [30]. An automatic equation and simulationbased methods for circuit sizing by considering layout effects is proposed. In this method, multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as optimizer. An automated method is adopted for placement and routing in analog layout generation using MOEA/D Both parasitics and geometrical information of the layout are regarded in the proposed method. In the MOEA/D, a scalar function is used to decompose a multi-objective optimization problem into a number of scalar optimization sub-problems In this method, optimization is performed simultaneously by the evolutionary algorithm. It should be mentioned that each optimal solution of (2) is a Pareto optimal solution of problem (1)

Placement
Routing
Parasitics Extraction
Circuit Sizing
Folded-cascode op-amp
Three-stage op-amp
Conclusions
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