Analog circuit fault analysis and feature extraction using hardware in loop simulation methodology using LabVIEW

Abstract

Analog circuits behavioral analysis are quite complex in comparison to digital circuits due to its non linear characteristics, making it difficult during fault analysis. Extracting the fault features will simplify such difficulties. Simulation Before Test (SBT) using computer-aided simulators is one of the traditional methods widely used in fault analysis. Due to computation and runtime limitations, this paper discusses fault analysis and feature extraction, using Hardware-In-Loop (HIL) simulation technique with a computer-based instrumentation tool. The circuit under test is modeled using a first-order differential equation, and output responses are derived using a numerical method-based differential equation solver and deployed in a Real-time Field Programmable Gate Array (FPGA) target for real-time simulation using LabView. Catastrophic failure is a major fault that occurs commonly in analog circuits. This paper concentrates on the circuit modeling and fault injection (simulation) in a DC-to-DC converter at steady state condition, to extract the fault feature using a real-time interactive HIL simulator. The fault scenarios are injected and the fault output responses are analyzed by comparing with a real-time fault output response.