Analog built-in saw-tooth generator for ADC histogram test

Abstract

This paper presents an analog built-in saw-tooth generator to be used for linear histogram test of ADCs. The internal generation of a highly linear signal with precise amplitude control relies on the use of an original calibration scheme. The effectiveness of the calibration procedure is evaluated through simulations and results demonstrate that ramp signals with a linearity of 15 bits and an average slope error of 0.4% can be achieved. In addition, the proposed implementation exhibits a very low silicon area, making the generator suitable for BIST application.