An upgraded ATLAS Central Trigger for post-2014 LHC luminosities

G Anders ,S Mättig ,P Farthouat ,R Spiwoks ,S Haas ,M Kaneda ,E Dobson ,D Berge ,T Wengler ,A Messina ,C Gabaldon ,B Gorini ,C C Ohm ,N Ellis ,M Dam ,T Pauly ,Ruth Pöttgen ,J T Childers ,H Bertelsen ,S Xella

doi:10.1088/1748-0221/8/02/c02031

Abstract

In early 2012, the Large Hadron Collider (LHC) reached instantaneous luminosities of 6.7·1033 cm−2s−1 and produced events with up to 40 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS trigger in order to reduce the collision rate of up to 40 MHz when operating with design parameters to a manageable event storage rate of about 400 Hz without discarding those events considered interesting. The Level-1 trigger is the first rate-reducing step in the ATLAS triggerand primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS detectors.After 2014, the LHC will run at a centre of mass energy of up to 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 1034 cm−2s−1. With higher luminosities, the required number and complexity of Level-1 triggers will increase in order to satisfy the physics goals of ATLAS while keeping the total Level-1 rates at a maximum of 100 kHz. To provide this added functionality, the Central Trigger Processor will be upgraded during the planned LHC shutdown that begins in 2013.

Highlights

The Central Trigger Processor (CTP) [4] is implemented in custom-built VME electronics
The CTPMI board, the interface to the Large Hadron Collider (LHC) [5], receives the timing signals from the LHC. These signals are the bunch crossing clock (BC) and the orbit signal which is issued with the beam revolution frequency
The trigger signals from the sub-detectors arrive at three input boards (CTPIN), each of which accepts 4x31 inputs that are synchronised, aligned and monitored with scalers. 160 input signals are selected by a switch matrix and transmitted via the Pattern In Time (PIT) bus to the CTPCORE board, which forms the L1A, and to the CTPMON board for per-bunch monitoring

Summary

Hardware Overview

The Central Trigger Processor (CTP) [4] is implemented in custom-built VME electronics. The CTPMI board, the interface to the LHC [5], receives the timing signals from the LHC These signals are the bunch crossing clock (BC) and the orbit signal which is issued with the beam revolution frequency. The trigger signals from the sub-detectors arrive at three input boards (CTPIN), each of which accepts 4x31 inputs that are synchronised, aligned and monitored with scalers. 160 input signals are selected by a switch matrix and transmitted via the Pattern In Time (PIT) bus to the CTPCORE board, which forms the L1A, and to the CTPMON board for per-bunch monitoring. The physics bunch group, for example, consists of those bunch crossing IDs where the two beams meet in ATLAS These bunch groups can be used in a logical AND with the other trigger conditions. Following protective dead-time rules or on request by sub-detectors, the CTP can veto triggers. The sub-detectors can send calibration requests to the CTPCAL module via the calibration bus

Current Operation

Upgrade plans for 2014