An ultra-low power high-order temperature- compensated CMOS voltage reference

Abstract

This work presents an ultra-low power low-voltage high-order temperature-compensated voltage reference. The proposed circuit is based on the self-cascode MOSFET (SCM) and explores the dependence of the threshold voltage (V T ) with the transistor dimensions. The SCM is biased by the leakage current of a zero-V T transistor for PSRR improvement. The proposed circuit is composed only of 3 transistors. The high-order temperature compensation is achieved through a bulk-driven scheme. Additionally, the proposed high-order compensation also attenuates the mismatch variability of the voltage reference. Post-layout simulation results for a standard 130 nm CMOS process are presented. A voltage reference of 90.5 mV with a 1 ppm/°C temperature coefficient (TC) is achieved at typical corner. The circuit can operate at a minimum supply voltage as low as 0.3 V while consuming 43.7 pW at room temperature.