An ultra-low power asynchronous quasi-delay-insensitive (QDI) sub-threshold memory with bit-interleaving and completion detection

Abstract

We propose a 256×8-bit ultra-low power asynchronous memory design with emphases on micropower, improved soft errors, and operation robustness (i.e. innately self-timed operation which can tolerate Process, Temperature, and Voltage variations) for sub-threshold operation (i.e. the supply voltage V DD is below the threshold voltage of transistors). The proposed memory, to the best of our knowledge, is the first asynchronous memory appropriate not only for bit-interleaving to reduce the impact of soft error, but also for robust full dynamic voltage range operation (from nominal to near-threshold to sub-threshold voltage operation). These attributes a re achieved in several ways. First, the 4-phase dual-rail a synchronous quasi-delay-insensitive (QDI) implementation is employed. Second, a Write Completion Detector and Read Completion Detector are proposed to respectively monitor the computation time required for a write and a read operation. Third, a novel 11-transitor memory cell embodying decoupled read buffers is proposed to improve read static-noise-margin (SNM) and applicable for bit-interleaving. The proposed memory is realized using a 130nm CMOS process, and we show that it can operate robustly from 0.2V to 1.2V, dissipates 96.7nW @ (0.2V, 2 kHz), and operate at average speed of 8.7µs @ 0.2V.