An ultra-low power amplifier for wearable and implantable electronic devices

Abstract

This paper presents an ultra-low-power CMOS amplifier for Low-frequency biosignal recording applications, especially for implantable biosensors and wearable or portable devices such as wearable electrocardiogram (ECG) recording microsystems that power consumption and on-chip area are the critical constraints. The proposed amplifier consists of two stages. In the first stage, a current reuse topology is used to achieve a lower input-referred voltage noise power density compared to a normal single-ended common source amplifier. In order to reduce the on-chip area, an inverter based amplifier with high output impedance is used at the output stage of the circuit to reduce the area occupied by the large load capacitance, which is required for having low cut off frequency of 200 Hz. Using this technique, the required load capacitance is decreased to about 2.1 pF. To reduce the power consumption, a ± 0.6 V supply voltage is used, and the transistors are pushed toward sub-threshold region to reduce the bias currents to about 260 nA in the first and the second stages. To validate the design, the proposed amplifier is simulated using 0.18 μm TSMC CMOS technology with Cadence in post-layout level. It is shown that the total power consumption of the proposed amplifier is as low as 640 nW. The proposed amplifier benefits from a CMRR >125 dB, total input-referred noise of 6.1 μVrms in 200 Hz bandwidth for ECG signal recording, and a closed-loop gain of about 35.1 dB. The layout of the circuit occupies a total area of 0.034 mm2.