An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits

Abstract

In this brief, a standard cell library targeting ultra-low voltages (ULVs) is designed in a 65-nm low-power CMOS technology to enable digital integrated circuits (ICs) to achieve good tradeoff among speed, power consumption, area, and reliability in the near/subthreshold region. The transistor sizes in the standard cells are optimized by threshold voltage tuning and technology feature exploration to enhance the switching and area efficiency of transistors. To balance the pull-up and pull-down networks, a Monte Carlo (MC) simulation-based balancing method is proposed. An AES-128 test circuit is fabricated by using the proposed library, achieving a minimum voltage of 0.338 V. Compared to the state of the art, our test circuit reduces the minimum energy delay product (EDP) by at least <inline-formula> <tex-math notation="LaTeX">$3.55\times $ </tex-math></inline-formula>.