Abstract

Physical unclonable function (PUF) utilizes the unexpected intrinsic manufacturing process variations of device to generate unique bit streams for authentication, key generation and random number generation. It has emerged as a promising primitive to address various challenges in hardware security. Traditional PUF schemes, such as arbiter PUF and ring oscillator (RO) PUF, do not have efficient implementations on FPGA and thus limit their usage as FPGA becomes the dominate design platform for today's emerging applications. In this paper, we propose a novel look-up table (LUT) shift register (SR) based PUF scheme for FPGA. This PUF incurs ultra1-low resource overhead, only two SLICEs to produce a 128-bit signature in our experimentation on XILINX Virtex-5 FPGA. Meanwhile, the PUF response are good in terms of uniqueness and robustness. At the same temperature, the proposed PUF has a 99%+ reliability on its response. When temperature changes between 25°C and 75°C, the robustness drops, but is still over 90%.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.