An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process

Abstract

The ultra-low power circuits are widely applied in energy-effective systems. This paper proposes a multi-valued adiabatic logic (MVAL) technique for energy-efficient using multiple threshold transistor and switch-level circuit. The multiple thresholds Literal Gate based on High-VTH and Low-VTH transistors are utilized to control pass-gate of adiabatic logic circuit. The presented MVAL hardware architecture can be used to energy-efficient and area reduction. Apart from the MVAL function, the proposed method supports multi-valued units with logic 0, 1, 2. The energy-effective and multi-valued adiabatic logic multiplier is implemented in 65 nm CMOS process. The core size of the chip occupies 0.32 mm2. The full-custom designed multiplier operates at alternating current (AC) power supply. It consumes 110 pW under 1.2 V supply at 300 MHz. Compared with other state of the art, the power dissipation decreases about 45%.