An ultra high step‐up DC‐DC converter based on VMC, POSLLC, and boost converter

Abstract

In this article, an ultra-high step-up DC-DC converter has been proposed. The topology of the converter is a combination of a cascaded boost converter, positive output super lift Luo converter (POS LLC), and a voltage multiplier cell (VMC). The lower values of the duty cycle provide a more than 10 times voltage gain. Consequently, the high voltage gain has been provided beside the lower value of the voltage/current stress of the semiconductor and an acceptable value of the efficiency. With a detailed look, it can be understood the voltage gain and efficiency of the converter have become 12 times and 90.5% based on the experimental results while the percentage of the duty cycle has become 50%. Moreover, by the mentioned percentage of the duty cycle, the normalized value of the voltage/current stress of the semiconductors has become lower than 50% by exception of only 3 semiconductor-based components which have voltage/current stresses more than 50% and lower than the unity. In addition to all the mentioned advantages, the input current has remained continuous which solves the challenges of the input filter's capacitor. Moreover, the voltage/current stresses have been kept low-valued. The ideal mode of the topology has been discussed for both continuous/discontinuous current modes. The non-ideal mode of the topology and its related comparisons have been done. A comparison of the voltage/current stresses of the semiconductor-based components has been done. Moreover, the comparison of the losses and efficiency have been done for the proposed converter and recently suggested topologies. In addition, the efficiency has been discussed for the different values of its effective factors and the resulted behavior has been expressed. Finally, the simulation and experimental outcomes have been extracted for a 120 W output power and compared with the theoretical relations' results.