An S-Band CMOS 6-Bit Vector-Sum Phase Shifter with Low RMS Phase Error Using Frequency-to-Voltage Converter Feedforward Loop

Abstract

In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2–4[Formula: see text]GHz) applications. The designed phase shifter in 180[Formula: see text]nm CMOS technology achieves an RMS phase error in the range of 0.607–1.18∘ with [Formula: see text][Formula: see text]dBm input signal over 2–4[Formula: see text]GHz frequency band. With lower input signal of [Formula: see text][Formula: see text]dBm, the RMS phase error is 0.621–1.34∘ for 2–4[Formula: see text]GHz input frequency. The proposed phase shifter shows an RMS amplitude error less than 0.41[Formula: see text]dB over 2–4[Formula: see text]GHz frequency. The 1-dB compression point ([Formula: see text]) of the proposed phase shifter is [Formula: see text][Formula: see text]dBm. The proposed wideband phase shifter draws 32 mA from 1.8 supply voltage. It occupies an active area of only 0.025[Formula: see text]mm2, due to active design without any inductor.