Abstract
RRAM is an emerging technology with vast applications in computation and storage. RRAM with MLC capabilities is more interesting owing to its higher storage density. In this study, we proposed an approach for RRAM-based MLC design. The approach starts with capacitor-based quantization of electric charge applying to RRAM. Numerical characterizations of a unit-circuit, including RRAM, capacitor and one MOS transistor were used. Two Stanford and Peking-Stanford RRAM models were employed in this study. The proposed design results in simplified circuitry and avoids power hungry elements (e.g. Op-Amp). A detailed RRAM-based MLC memory array is implemented. To simplify the memory read process, a TIQ-ADC is employed. To evaluate the approach, circuit-level mixed SPICE/Verilog-A simulations were performed. The variation and random effects are experimented using Monte-Carlo simulations. The costs of the proposed approach are design-time pre-computation and complexity of one-time device characterization.
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