Abstract
Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes a RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, a RISC-V processor with area-efficient memristor-based IMC was developed based on an open-source core for IoT applications, Hummingbird E200. The general compiling policy with the data allocation method is also disclosed for the IMC implementation of the Keccak hash algorithm. An evaluation shows that >70% improvements in both performance and energy saving were achieved with limited area overhead after introducing IMC in the RISC-V processor.
Highlights
Internet of things (IoT) refers to the network of different physical devices, which enables them to collect and exchange data [1,2]
The control and operation module in Verilog hardware description language (HDL) format was firstly compiled by a Synopsys design compiler to acquire the equivalent gate count, which was multiplied by the size of two-input NAND gate, i.e., NAND2, in the 28-nm process to get the corresponding area
The hash function used in blockchain helps to ensure information security, as well as data integrity
Summary
Internet of things (IoT) refers to the network of different physical devices, which enables them to collect and exchange data [1,2]. Secure, and private nature, the blockchain can enable secure messaging between devices in an IoT network. In this approach, the Micromachines 2019, 10, 541; doi:10.3390/mi10080541 www.mdpi.com/journal/micromachines. The data transfer on the bus between the central processing unit (CPU) and the memory leads to large power consumption and limited performance, i.e., memory bottleneck. To address this issue, IMC modififies the memory to be able to perform some regular logic operations such as AND, OR, and exclusive or (XOR) [9].
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
