Abstract
A resistor-coupled Josephson logic (RCJL) [1] decoder was proposed and experimentally tested to satisfy the requirements for a Josephson cache memory. The RCJL decoder is an ac powered latch decoder and is constructed from RCJL AND-OR units. Therefore, it has advantages in regard to higher packing density, reduced decoding time, and intrinsically damped resonance phenomena over interferometer decoders. A 4-bit decoder, consisting of 28 AND-OR units, was fabricated using a 4-µm Pb-alloy technology. A ±14- percent gate-bias-current margin was obtained.
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