An optimized FPGA architecture for machine learning applications

Abstract

FPGAs are currently the most suitable hardware accelerators to implement and accommodate the non-stop growth of machine learning applications. This paper presents an FPGA architecture with added posit multipliers that outweigh the current IEEE-754 multipliers in terms of delay and area. Since machine learning algorithms involve a lot of expensive mathematical operations, having such powerful multipliers in the proposed FPGA architecture will execute the needed operations with high efficiency, which will stand out for machine learning applications without compromising other FPGA applications. Experimental results using Verilog to Routing (VTR) on both machine learning and non-machine learning benchmarks have demonstrated that our proposed architecture consumes 10% less area than the Stratix IV FPGA. Furthermore, it consumes less power compared to both the Stratix IV and Stratix 10 FPGAs, with reductions of 22% and 10%, respectively. Additionally, our architecture outperforms the Stratix IV and Stratix 10 FPGAs in terms of critical path delay, with improvements of 25.5% and 43%, respectively.